Prior art VCO circuits use a replica bias circuit to limit the voltage swing in current-controlled differential amplifier stages of the VCO. The frequency of a current-controlled VCO is directly proportional to the current through the differential amplifier stages of the VCO. The frequency of a current-controlled VCO is inversely proportional to the circuit capacitance and to the voltage swing in the differential amplifier stages. In order to provide a linear frequency-versus current characteristic, it is desirable to keep the voltage swing a constant. A replica bias circuit is used to control the voltage swing of the differential amplifier stages of the VCO. The replica bias circuit is a feedback loop circuit which uses a high gain operational amplifier and a reference MOS transistor with the same characteristics as the load transistors of the differential amplifier stages of the VCO. The replica bias circuit is configured so that the gate voltages, the drain voltages, and the currents of the reference MOS transistor and the load transistors of the differential amplifier stages are the same. An external bias voltage applied to one input terminal of the operational amplifier controls the output amplitude swings of the differential amplifier stages of the VCO.
The voltages at the gates of the load transistors of the differential amplifier stages are not bypassed at high frequencies. The load transistors of the differential amplifier stages are subject to all of the noise signals caused by the active circuitry of the feedback loop formed by the high gain operational amplifier and the reference MOS transistor.
Also the feedback loop of the replica bias circuit is difficult to stabilize over a wide range of VCO control voltage inputs, which produce a wide range of control currents. The currents through the VCO differential amplifier stages are changed to control the delays through each stage. The changes in delays vary the frequency of oscillation of the VCO.
It may be shown that if the operational amplifier of the replica biasing feedback loops is a 2 stage internally compensated amplifier, the replica bias feedback loop will become unstable at low drain currents through the reference MOS transistor when the gate voltage of the reference MOS transistor is low and the reference MOS transistor is in a high gain saturation region with extra gain and phase shift which causes the feedback control loop to become unstable. When the loop control voltage is low, the VCO frequency is low and instability occurs. Low frequency jitter increases until the phase lock loop loses lock. This makes a targeted VCO frequency range much more difficult to obtain over variations in process parameters, temperature, and supply voltages. For lower supply voltages, these problems are worse because the stable linear region range for the gate voltages of the load transistors of the differential amplifier stages is smaller. For example, with the feedback loop replica biasing scheme as described above, the load transistors of the differential amplifier stages are in their linear regions with gate-to-source voltages greater than 2 volts.
Thus, a need exists for low noise, low voltage, stable amplifier stages for the VCO of a phase lock loop.